Hereinafter, a conventional parallel type A/D converter will be described.
FIG. 24 is a diagram illustrating a conventional parallel type A/D converter 1200.
With reference to FIG. 24, the parallel type A/D converter 1200 has, as external inputs, an analog input signal AIN, an external input operation clock signal CKIN, and a start signal ST, and it comprises a reference voltage generation circuit 1201, a comparison circuit 1202, a logic circuit 1203, and a clock buffer circuit 1204.
The clock buffer circuit 1204 includes a plurality of inverters connected in series with each other, receives the external input operation clock signal CKIN, and generates an operation clock signal CLK_CMP for the comparison circuit and an operation clock signal CLK_ENC for the logic circuit by so-called inverter delay, i.e., by successively delaying the external input operation clock signal CKIN which is input to the first stages of the plural inverters connected in series with each other by these inverters.
Accordingly, the external input operation clock signal CKIN, the comparison circuit operation clock signal CLK_CMP, and the logic circuit operation clock signal CLK_ENC have completely the same signal elements such as frequency, amplitude, duty, jitter and the like.
However, the phase of the logic circuit operation clock signal CLK_ENC and the phase of the comparison circuit operation clock signal CLK_CMP are inverted from each other.
The operation of the conventional parallel type A/D converter is described in Embodiment 1 of Patent Document 1.
FIG. 25 is a diagram illustrating the configuration of an A/D converter 1200 according to Embodiment 1 of Patent Document 1.
As shown in FIG. 25, the A/D converter 1200 includes a reference voltage generation circuit (reference voltage generation means) 1201, a differential amplifier line (differential amplification means) 112, and an operation circuit (operation means, comparison circuit) 1202.
This A/D converter 1200 may further include an encoding circuit (coding means, logic circuit) 1203.
The reference voltage generation circuit 1201 generates a plurality of reference voltages VR1 to VRm+1 by a plurality of resistors R1 to Rm (m: an integer not less than 2) for voltage division which are connected in series with each other. The reference voltage VRm+1 is obtained from a tap which is connected to a high voltage (power supply voltage) applying node 1201a and to a resistor Rm, the reference voltage VRi (i=2, . . . , m) is obtained from a tap which is connected between a resistor Ri−1 and a resistor Ri, and a reference voltage VR1 is obtained from a tap which is connected to a low voltage (ground voltage) applying node 1201b and to a resistor R1.
The differential amplifier line 112 includes m+1 pieces of differential amplifiers A1 to Am+1, and amplifies voltage differences between the respective reference voltages VR1 to VRm+1 and an input analog signal voltage Ain supplied from an analog signal voltage input terminal 104 to generate a plurality of output voltage sets.
Each of the plural output voltage sets includes a complementary noninverted output voltage and an inverted output voltage.
The noninverted output voltages and the inverted output voltages which are included in the output voltage sets supplied from the differential amplifiers A1 to Am+1 are directly outputted to comparison circuits Cr1 to Crn+1 in the operation circuit (comparison circuit) 1202.
The operation circuit (comparison circuit) 1202 includes n+1 pieces of comparison circuits (comparison means) Cr1 to Crn+1, and each of the comparison circuits Cr1 to Crn+1 has four inputs. The comparison circuits Cr1 to Cr4 receive the noninverted output voltages and the inverted output voltages from the differential amplifiers A1 and A2, the comparison circuits Cr5 to Cr8 receive the noninverted output voltages and the inverted output voltages from the differential amplifiers A3 and A4, . . . , and the comparison circuits Crn−2 to Crn+1 receive the noninverted output voltages and the inverted output voltages from the differential amplifiers Am and Am+1. That is, every four comparison circuits receive the noninverted output voltages and the inverted output voltages from two differential amplifiers placed at both ends thereof. The operation circuit (comparison circuit) 1202 receives the plural output voltage sets, and operates according to a clock signal.
Each of the comparison circuits Cr1 to Crn+1 has an input transistor part and a positive feedback part. The first output voltage set and the second output voltage set among the plural output voltage sets are input to the input transistor part. The positive feedback part is operated according to the clock signal.
Then encoding circuit 1203 encodes the comparison result (digital signal) to generate a digital data signal.
In this way, in the conventional parallel type A/D converter 1200, the reference voltage generation circuit 1201 comprises a plurality of resistors connected in series with each other as described above, and the higher voltage side reference voltage is connected to an end of the series-connected body while the lower voltage side reference voltage is connected to the other end thereof.
Then, the divided voltages of the reference voltages are outputted as the reference voltages from the plural connection nodes between the resistors.
In the differential amplifier line 112, each of the plural differential amplifiers has two input terminals, and the input analog signal voltage is input to one of the input terminals while one of the reference voltages is input to the other input terminal, and the differential amplifier outputs a noninverted output voltage and an inverted output voltage.
In the comparison circuit 1202, the input transistor part performs a predetermined weighted operation to the noninverted output voltage and the inverted output voltage from the differential amplifier to determine a threshold voltage, and outputs, to the positive feedback part, a comparison result obtained by comparing a difference between the first noninverted output voltage and the first inverted output voltage with a difference between the second noninverted output voltage and the second inverted output voltage.
The positive feedback part amplifies the comparison result outputted from the input transistor part when the clock signal is at a predetermined level, and outputs the amplified comparison result as a digital signal to the encoding circuit. This digital signal is, for example, a H-level or L-level digital signal according to the comparison result.
As described above, in the conventional parallel type A/D converter 1200 shown in FIG. 24, the external input operation clock signal is delayed and inverted by the clock buffer 1204 to generate the comparison circuit operation clock signal CLK_CMP and the logic circuit operation clock signal CLK_ENC.
Therefore, as shown in FIG. 26, when a clock having a duty ratio of 50% is used as the external input operation clock signal CKIN, the generated comparison period of the comparison circuit 1202 becomes equal to the initialization period of the logic circuit 1203.
Likewise, the initialization period of the comparison circuit 1202 becomes equal to the coding period of the logic circuit 1203, and thus A/D conversion is carried out.
As described above, in the conventional parallel type A/D converter, the comparison circuit operation clock signal CLK_CMP and the logic circuit operation clock signal CLK_ENC are generated by simply distributing the external input operation clock signal CKIN.
Therefore, the performances of the A/D converter such as maximum operation frequency and power consumption are undesirably determined by the characteristics of the external input operation clock signal CKIN such as duty, frequency, and jitter.
Further, since it is indispensable to supply the external input operation clock signal CKIN during the operation, a clock generator for supplying this clock signal takes cost and space.
Next, FIG. 27 is a diagram illustrating a conventional successive-approximation type A/D converter 1300.
In FIG. 27, the successive-approximation type A/D converter 1300 has, as external inputs, an analog input signal AIN, an external input operation clock signal CKIN, and a start signal ST, and comprises a reference voltage generation circuit 1301, a comparison circuit 1302, and a logic circuit 1303.
The operation of the conventional successive-approximation type A/D converter 1300 is described in Embodiment 1 of Patent Document 2.
FIG. 28 is a diagram illustrating the configuration of the A/D converter 1300 according to Embodiment 1 of Patent Document 2.
As shown in FIG. 28, the A/D converter 1300 has an analog input terminal 51 and an analog reference power supply terminal 52, and it is configured comprising a controller 1, inverters 1 to 6, 8, and 17 to 21, NAND circuits 7 and 9 to 16, transfer gates 22 to 32, capacitors 33 to 36 configuring a capacitor array, a comparator 1302, and a storage register 38.
Further, the reference voltage generation circuit 1301 in the A/D converter 1300 is configured comprising transfer gates 22 to 32, capacitors 33 to 36, and an inverter 21.
The transfer gates 24, 26, 28, 30 and the capacitors 33, 34, 35, 36 are connected in series with each other, and are connected between the ground and the noninverted input of the comparison circuit 1302. The noninverted input of the comparison circuit 1302 is grounded via the transfer gate 32.
Further, one ends of the transfer gates 25, 27, 29, 31 are connected to the connection nodes of the transfer gates 24, 26, 28, 30 and the capacitors 33, 34, 35, 36 while the other ends thereof are connected to each other and to the analog reference power supply terminal 52 and the analog input terminal 51 via the transfer gates 22 and 23.
Further, the successive-approximation logic circuit 1303 in the A/D converter 1300 is configured comprising a controller 1, inverters 2 to 6, 8, 17 to 20, and NAND circuits 7 and 9 to 16.
END of the controller 1 is connected to one inputs of the NAND circuits 7 and 9 to 16 via the inverter 6. The control signals S1, S2, S5, S7, and S9 of the controller 1 are connected to the other inputs of the NAND circuits 7, 9, 12, 14, and 16, and the control signals S3, S4, S6, and S8 of the controller 1 are connected to the other inputs of the NAND circuits 10, 11, 13, and 15 via the inverters 2, 3, 4, and 5, respectively.
The output of the NAND circuit 7 is connected to the control inputs of the transfer gates 23 and 32 via the inverter 8, and the output of the inverter 8 is connected to the control input of the transfer gate 22 via the inverter 21. Further, the outputs of the NAND circuits 10, 11, 13 and 15 are connected to the control inputs of the transfer gates 25, 26, 28, and 30, and the outputs of the NAND circuits 9, 12, 14, and 16 are connected to the control inputs of the transfer gates 24, 27, 29, and 31 via the inverters 17, 18, 19, and 20, respectively.
The relative capacitance ratios of the capacitors 33(capacitance C1), 34(capacitance C2), 35(capacitance C3), and 36(capacitance C4) are set as shown in the following formula:C1:C2:C3:C4=1:1/2:1/4:1/4  (1)
Further, FIGS. 29(a),(b),(c),(d),(e),(f),(g),(h),(i),(j), and (k) are timing charts showing the operation signals used in Embodiment 1 of Patent Document 2.
Next, the operation of Embodiment 1 of Patent Document 2 will be described with reference to the block diagram shown in FIG. 28 and the timing charts shown in FIGS. (a),(b),(c),(d), (e),(f),(g),(h),(i),(j), and (k).
As for the timings of the control signals S1 to S9 and the END signal which are outputted from the controller 1, the timings are similar to those described in Prior Art (refer to FIG. 31) of Patent Document 2.
Initially, during a sample period T1 (refer to FIG. 31), the output levels of the control signals S1, S3, S5, S7 and S9 outputted from the controller 1 are “HIGH”, and the transfer gates 67, 69, 71, 73 and 75 are in their ON states.
Further, the output levels of the control signals S2, S4, S6 and S8 outputted from the controller 1 and the output level of the inverter 77 are “LOW”, and the transfer gates 66, 68, 70, 72 and 74 are in their OFF states, and thereby the analog signal inputted through the analog input terminal 55 is transferred through the transfer gates 75, 67, 69, 71 and 73 to the capacitors 78, 79, 80 and 81, and thus charging and discharging of the capacitors are carried out.
Thereby, sampling of the analog values of the analog signal is carried out.
During a hold period T2 that follows the above-described sampling period, the output levels of the control signals S1, S3, S5, S7 and S9 outputted from the controller 1 are “LOW”, and the transfer gates 67, 69, 71, 73 and 75 are in their OFF states, and the electric charges which were taken in during the sampling period T1 are held by the capacitors 78, 79, 80 and 81.
The voltage V of the compare line which is input to the comparator 37 at this time is represented by the following formula, with the level of the analog voltage inputted to the analog input terminal 55 being Vi.V=−Vi  (2)
Next, the A/D conversion operation takes place. Initially, in the first state of the conversion operation, the output level of the control signal S3 becomes “HIGH” in the controller 1 and thereby the transfer gate 67 is turned on. Thereby, the level of the reference voltage Vr which is supplied from the analog reference power supply terminal 56 is applied to one terminal of the capacitor 78.
Since the capacitance C1 of the capacitor 78 is ½ of the total capacitance value of the capacitors C1 to C4, the voltage V of the compare line inputted to the comparator 37 is given by the following formula:V=−Vi+Vr/2  (3)
In this formula (3), when V<0, the output level of the comparator 37 which is transferred to the controller 1 becomes “0”, and the output level of the control signal S3 which is outputted from the controller 1 is maintained at “HIGH”, and thereby the transfer gate 67 remains in its ON state, and the most significant bit is set to “1”.
On the other hand, when V>0, the output level of the comparator 37 becomes “HIGH”, and the output level of the control signal S2 outputted from the controller 1 becomes “HIGH” while the output level of the control signal S3 becomes “LOW”, and thereby the transfer gate 66 is turned on while the transfer gate 67 is turned off, and thus the most significant bit is set to “0”.
Thereby, in FIG. 31, “HIGH” is set at the most significant bit in the state where the output level of S2 is “LOW” and the output level of S3 is “HIGH”.
Next, the 2nd bit from the most significant bit is determined. In the controller 1, the output level of the control signal S5 is set to “HIGH” to turn on the transfer gate 69, and thereby the voltage V of the compare line inputted to the comparator 37 becomes a voltage which is represented by one of the following two formulae according to the state of the already-set most significant bit.V=−Vi+Vr/2+Vr/4 (when the most significant bit is “HIGH”)  (4)V=−Vi+Vr/4 (when the most significant bit is “LOW”)  (5)
In the example shown in the timing chart of FIG. 31, since the most significant bit is set at “HIGH”, the voltage V of the compare line is represented as follows:V=−Vi+Vr+Vr/4  (6)
Also in this case, as in the case of determining the most significant bit, the 2nd bit from the most significant bit is set to “HIGH” by the comparator 37 and the controller 1 when V<0, and it is set to “0” when V>0. When the bits up to the least significant bit are determined in similar procedure, the voltage of the compare line is sorted to any of eight states from (1111) to (0000). In the timing chart of FIG. 31, it is finally (1100).
Next, in the state where the A/D conversion has been completed as described above and the conversion result is written in the storage register 38, the level of the END signal outputted from the controller 1 changes from “LOW” to “HIGH” in the successive-approximation type A/D converter 1300 of Embodiment 1 of Patent Document 2.
The A/D conversion result is written in the storage register 38 by the control function due to this END signal, and the output level of the inverter 6 changes from “HIGH” to “LOW”, and thereby all the output levels of the NAND circuits 7 and 9 to 16 become “HIGH”.
Thereby, all the gates of the transfer gates 22, 25, 26, 28 and 30 are turned on while all the gates of the transfer gates 23, 24, 27, 29, 31 and 32 are turned off by the inversion functions of the inverters 8 and 17 to 21.
In this case, the total charge capacitance Q in the capacitors 33 to 36 is initialized as represented by the following formula:Q=C1·Vr  (7)
Accordingly, in the sampling state of the next A/D conversion which is subsequently performed, all the gates of the transfer gates 22, 24, 26, 28 and 30 are turned off.
Further, the respective gates of the transfer gates 23, 25, 27, 29, 31 and 32 are all turned on, and the voltage level Vo in the B line at starting the sampling is represented by the following formula:Vo=Vr·C1/(C1+C2+C3+C4)=Vr/2  (8)
Accordingly, during the sampling of the analog voltage values applied to the analog input terminal 101 which are held by the capacitors 33 to 36, since charging or discharging is always performed from the level of Vr/2 regardless of the charge capacitance that is sampled/held in the previous conversion, constant A/D conversion characteristics are obtained for the analog input voltage of the constant level.
Further, the maximum charge amount to be charged or discharged for the capacitors 33 to 36 is within the range from maximum 0 to Vr level in the conventional case, it is within the range from 0 to Vr/2 or from Vr/2 to Vr in Embodiment 1 of Patent Document 2, and therefore, the charge amount is reduced to ½.
Accordingly, when the sampling period is equal to that of the conventional example, it is possible to double the allowable value for the resistance value connected to the analog input terminal 101. Further, when the resistance value connected to the analog input terminal is equal to that of the conventional example, the length of the sampling period can be reduced to ½.
That is, the reference voltage generation circuit 1301 has a plurality of capacitors which are connected in parallel with each other and have the capacitance ratios set at 1:1/2:1/4:1/4, and the successive approximation logic circuit 1303 performs sampling by connecting the analog input signal AIN to one ends of the plural capacitors during the sampling period.
In the next hold period, the successive approximation logic circuit 1303 separates all the capacitors from the ground to hold the taken-in charges.
The operation timing of the successive approximation type A/D converter shown in FIG. 27 is shown in FIG. 32.
In the configuration of the successive approximation type A/D converter 1300, as shown in FIG. 32, an initialization period, a comparison period, and a coding period are generated by the external input operation clock signal CKIN, and A/D conversion is carried out.
Accordingly, the performance of the conventional successive approximation type A/D converter 1300 is determined depending on the characteristic of the external input operation clock signal CKIN, like the conventional parallel type A/D converter 1200, and it is indispensable to supply the external input operation clock signal CKIN during the operation.    Patent Document 1: Japanese Published Patent Application No. 2003-158456    Patent Document 2: Japanese Published Patent Application No. Hei.5-259913